Conventional pulse shaper presented in `IEEE Transactions on Communication Technology`, Vol. COM-16, No. 1, February, 1968, pp 81-93, is comprised of a resistor arrangement, digital input controlled shift register, and a summing node. The disadvantages of such pulse shaper are that only one polarity output signal can be generated and requires too many resistors.
The pulse shaper presented in U.S. Pat. No. 4,814,637, named `pulse shaper,` is a well known pulse shaper for ISDN U-interface. The pulse shaper disclosed in U.S. Pat. No. 4,814,637 includes a control signal generator, a summing network including a number of charging capacitors, a controll able switch arrangement, a plurality of logic circuits coupled between the control signal generator and respective ones of the controllable switch arrangement. The respective charging capacitor associated with a respective switch exchanges a component charge with the summing capacitor that corresponds to the step to be formed on the occurance of the particular control signal. The main disadvantage of such pulse shaper is that it requires a series of complex switch topology and as many number of charging capacitor as the steps of the one output staircase-type slope.